The invention relates to semiconductor packaging and, in particular, to an integrated capacitor on a packaging substrate.
Since the operating speed of packaged circuits is concerned with the evaluation of power planes, the voltage stability of power planes is critical during operation of high frequency/high speed circuits. When many output drivers switch simultaneously, large currents crowd, into a ground end or power supply end, thus generating simultaneous voltage change in the power distribution of a chip or packaged sample. This simultaneous switch causes a simultaneous voltage difference between the ground potentials of an internal chip ground and a system ground. The offset of the ground potential is a simultaneous switching noise, which is expressed as V=L(di/dt). The voltage change of the simultaneous switching noise is proportional to inductances coupled to power and a rate of current change. Since semiconductor circuits have become more integrated, larger inductance is induced on longer routings. The simultaneous switching noise also becomes more prominent.
To overcome the simultaneous switching noise issue, decoupling capacitors are traditionally disposed at specific locations on power planes in packaging substrate design. The decoupling capacitors are typically chip-type capacitors such that an impact on power planes can be minimized during operation of high frequency/high speed circuits.
However, additional discrete chip-type capacitors increase packaging cost and failure probability, resulting in diminished reliability.